PT7M7443-52,PDF数据表下载

PT7M7443-52 pdf资料下载The PT7M7443~7452 low-current microprocessor reset circuits feature single or dual manual reset inputs with an extended 6.72s setup period. Because of the extended setup period, short switch closures (nuisance resets) are ignored. On all devices, the reset output asserts when any of the monitored supply voltages drops below its specified threshold. The reset output remains asserted for the reset timeout period (210ms typ) after all monitored supplies exceed their reset thresholds. The reset output is one-shot pulse asserted for the reset timeout period (140ms min) when selected manual reset input(s) are held low for an extended setup timeout period of 6.72s. These devices ignore manual reset transitions of less than 6.72s (typ). PT7M7443L PT7M7443M PT7M7443T PT7M7443S PT7M7443R PT7M7443Z PT7M7443Y PT7M7443W PT7M7443V PT7M7444L PT7M7444M PT7M7444T PT7M7444S PT7M7444R PT7M7444Z PT7M7444Y PT7M7444W PT7M7444V PT7M7445L PT7M7445M PT7M7445T PT7M7445S PT7M7445R PT7M7445Z PT7M7445Y PT7M7445W PT7M7445V PT7M7446L PT7M7446M PT7M7446T Datasheet pdf资料数据表下载